IEEE Transactions on Reliability Review Policy

IEEE Transactions on Reliability

Special Section on Hardware Security

Call for Papers


Due to escalating complexity of hardware design and manufacturing, integrated circuits (ICs) are usually designed and fabricated in multiple locations worldwide. With the utilization of third-party intellectual properties (IPs) and offshore foundries, the overall cost and time-to-market are significantly reduced. However, hardware security becomes more subject to various kinds of tampering in the IC supply chain. At the design stage, the malicious insertion of Trojan circuits as well as IC/IP privacy (theft) are the main threats to hardware security and trustworthiness; at the fabrication stage, there is the threat of cloning and overprocducing ICs at an offshore foundry; when the hardware is deployed, sensitive data can be extracted using hardware-based side channels, physical attacks, reverse engineering, etc. Over the past decade, hundreads of attacks have been reported and the number of attacks continues to rise.

In this special section, we solicit high-quality submissions related to hardware security. Specifically, we welcome papers that address the security issues across different stages in the IC supply chain and during the IC lifecycle. Submissions will be reviewed and selected based on innovation, practical relevance, technical correctness and presentation.


We welcome submissions in, but not limited to, the following topic areas:

  • IC/IP protection against piracy and overproduction
  • Hardware Trojan detection and isolation
  • Side channel attacks and countermeasures
  • Physical attacks and countermeasures
  • Trustworthy manufacturing, e.g., split manufacturing
  • Non-destructive reverse engineering
  • Recycling, remarked, out-of-spec ICs
  • Hardware security primitives: PUFs and TRNGs

Submission Information

We welcome high-quality submissions that are original work, not published, and not currently submitted elsewhere. We also encourage extensions to conference papers, unless prohibited by copyright, if there is a significant difference in technical content. Improvements such as adding a new case study or including a description of additional related studies do not satisfy this requirement. A description explaining the differences between the conference paper and the journal submission is required. The overlap between each submission and other articles, including the authors' own papers and dissertations, should be less than 30%.

All submitted papers will undergo a rigorous peer-review process and must conform to the double-column, the single-spaced format of printed articles in the IEEE Transactions on Reliability with all figures and tables embedded in the paper, rather than listed at the end or in the appendix. Refer to the special guidelines posted at

Important Dates

  • Submission Deadline:
  • 05/31/2025, rolling review and publication
  • Publication Date:
  • Rolling


    • Professor Winston Shieh
      Department of Computer Science, National Yang Ming Chiao Tung University, Taiwan

    Guest Editors

    • Professor Kai-Chiang Wu
      Department of Computer Science, National Yang Ming Chiao Tung University, Taiwan
    • Professor Siddharth Garg
      Department of Electrical and Computer Engineering, New York University, USA
    • Professor Yier Jin
      Department of Electrical and Computer Engineering, University of Florida, USA
    • Professor Hussam Amrouch
      Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
    • Professor Sying-Jyan Wang
      Department of Electrical Engineering, National Chung Hsing University, Taiwan